1 standard ics lcd driver for segment-type lcds BU9728AKV the BU9728AKV is a segment-type lcd system driver which can accommodate microcomputer control and a serial interface. an internal 4-bit common output and lcd drive power supply circuit enable configuration of a display sys- tem at low cost. applications movie projectors, car audio systems, telephones features 1) serial interface. (8-bit length) 2) display ram: internal, 128 bits. (up to 128 seg- ments can be displayed) 3) internal power supply circuit for lcd drive. 4) display duty: 1 / 4 5) can be driven with low voltage and low current dissi- pation. absolute maximum ratings (ta = 25?, v ss = 0v) parameter symbol limits unit v dd ?0.3 ~ + 7.0 v v lcd ?0.3 ~ + v dd v pd 400 * mw tstg ?55 ~ + 125 c topr ?20 ~ + 75 c power supply voltage 1 power supply voltage 2 power dissipation operating temperature storage temperature * reduced by 4.0mw for each increase in ta of 1 c over 25 c . recommended operating conditions (ta = 25?, v ss = 0v) parameter v dd 2.5 5.5 v v lcd 0v dd v the following relationship should be maintained: v dd ^ v 1 ^ v 2 ^ v 3 ^ v ss . r f = 470k w f osc khz 36 symbol min. typ. max. unit conditions power supply voltage 1 power supply voltage 2 (v dd - v 3 ) oscillation frequency
2 standard ics BU9728AKV block diagram serial interface display data ram (dd ram) lcd driver bias circuit lcd segment driver 32bits lcd common driver 4bits sd sck c / d cs reset v dd v 1 v 2 v 3 v ss com 0 com 1 com 2 com 3 seg 0 seg 1 seg 31 osc 1 osc 2 timing generator address counter common counter command decoder command / data register pin assignments seg 20 seg 21 seg 22 seg 23 seg 24 seg 25 seg 26 seg 27 seg 28 seg 29 seg 30 seg 31 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 seg 19 seg 18 seg 17 seg 16 seg 15 seg 14 seg 13 seg 12 seg 11 seg 10 seg 9 seg 8 osc 1 osc 2 v 1 v 2 v 3 v ss v dd sck sd cs c / d com 0 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg 1 seg 0 reset com 3 com 2 com 1 25 26 27 28 29 30 31 32 33 34 35 36 12 11 10 9 8 7 6 5 4 3 2 1 BU9728AKV
3 standard ics BU9728AKV pin descriptions osc 1 osc 2 1 2 i o sd 9 i cs 10 i i sck 8 v 1 ~ v 3 3 ~ 5 v ss 6 v dd 7 c / d 11 i com 0 com 3 12 ~ 15 o reset 16 i seg 0 seg 31 17 ~ 48 o pin no. i / o pin name function input / output pins for the internal oscillator. resistance is connected between these pins when the internal clock is running. when an external clock is running, the clock is input from osc 1 and osc 2 is left open. this is the reset input pin. when this pin is low, the BU9728AKV is initialized. it resets the address counter and turns the display off. this is the serial data input pin, used to input display data and commands. display data is displayed when this is "1" and not displayed when it is "0". this is the chip select signal input pin. when this pin is low, sd input can be received. the sck counter is reset when the cs pin goes from high to low. this signal detects whether the sd input is command or display data. if the pin is low at the rising edge of the 8th sck pulse, the input is recognized as display data, and if high, the input is recognized as command data. these are power supply pins for lcd drive. the following relationship must be satisfied: v dd ^ v 1 ^ v 2 ^ v 3 ^ v ss (low) . these are the segment output pins for lcd drive. they are connected to the lcd panel segments. these are the common output pins for lcd drive. they are connected to the lcd panel commons. this is the shift clock input pin for serial data. the contents of the sd pin are read one bit at a time at the rising edge of sck. this is the v ss power supply pin. this is the v dd power supply pin. input / output equivalent circuits v dd gnd gnd vdd v dd gnd gnd out v lcd v lcd in osc 1 in osc 2 i / o sd sck c / d cs i osc 1 osc 2 reset i i / o seg 0 seg 31 com 0 com 3 o ~ ~ pin name equivalent circuit pin name equivalent circuit
4 standard ics BU9728AKV electrical characteristics dc characteristics (unless otherwise noted, v dd = 2.5 ~ 5.5v, v ss = 0v, ta = 25?) parameter symbol min. typ. max. unit conditions pin input low level current 1 i il1 100 m av in = 0v input low level current 2 i il2 2 m av in = 0v input high level voltage v ih1 0.8 v dd v input low level voltage v il1 0 0.2 v lcd driver on resistance * 1 r on 30 k w d v on = 0.1v input high level current i ih ? 2 m av in = v dd input capacitance c in 5 pf reset reset osc 1 , sd, sck, c / d, cs osc 1 , sd, sck, c / d, cs reset seg 0 ~ 31 , com 0 ~ 3 osc 1 , sd, sck, c / d, cs, sd, sck, c / d, cs 0.05 1 m a in wait state * 2 when display is operating * 3 during access operation * 4 current dissipation i dd 40 80 m av dd 100 250 m a * 1 internal power supply impedance is not included in the lcd driver on resistance. * 2 all inputs, including v 3 = 0v and osc 1 , are fixed at either v dd or v ss . * 3 except for v 3 = 0v, rf = 470k w , and osc 1 , all inputs are fixed at either v dd or v ss . * 4 v 3 = 0v, rf = 470k w , f sck = 200khz v dd v dd ac characteristics (unless otherwise noted, v dd = 2.5 ~ 5.5v, v ss = 0v, ta = 25?) parameter symbol min. typ. max. unit conditions t cyc 800 ns t wait 800 ns t wh1 300 ns t tlh 100 ns t thl 100 ns t wl1 300 ns t su1 100 ns t h1 100 ns t wh2 300 ns t wl2 6400 ns * 5 only one (either one) of the conditions needs to be satisfied. t su3 100 ns t h3 100 ns t cch 100 ns t sch 100 ns t su2 100 ns t h2 100 ?s use rise for 8th ck of sck as standard use cs riss as standard use rise for 8th ck of sck as standard sck rise time sck fall time sck cycle time command wait time sck pulse width "h" sck pulse width "l" data setup time data hold time cs pulse width "h" cs pulse width "l" cs set-up time cs hold time c / d set-up time c / d hold time c / d - cs time * 5 c / d - sck time * 5
5 standard ics BU9728AKV timing charts t wl2 t su2 cs sck sd c / d t h2 t wh2 t cch t cyc t wh1 t wl1 t su1 t sch t h1 t tlh t thl t su3 t h3 fig.1 interface timing sck sd t wait t cyc d7 d6 d0 d7 fig.2 command cycle data format serial data is 4-line data transmitted in synchronization with the clock. serial data with a bit length of 8 bits is input in synchronization with sck. if c / d is high at the rising edge of the 8 nth sck clock pulse, the serial data is recog- nized as command data, and if c / d is low, the serial data is recognized as display data. serial data is input in sequential order, starting from the msb.
6 standard ics BU9728AKV a detailed look at commands the BU9728AKV has the following commands (c / d is high at 8 nth clock pulse of sck). (1) address set aaaaa and the address data displayed in binary format are set in the address counter. each time input of the display data (8 bits) has been completed, the address is incremented by + 2. (2) display on all display segments light, regardless of the contents of the display data ram (ddram). the contents of the ddram do not change. (3) display off all display segments go out, regardless of the contents of the ddram. the contents of the ddram do not change. (4) display start display begins, in accordance with the contents of the ddram. (5) rewrite display data ram (ddram) the binary bit data dddd is written to the ddram. the data is written to the address specified by the address set command, and after this command is executed, the address is automatically incremented by + 1. (6) reset this command should be executed before any other command, immediately after the power supply is turned on. this command resets the BU9728AKV to the following status: ?display is off ?address counter is reset 0 msb lsb 0 0 a a a a a 0 msb lsb 0 1 * * * * * * irrelevant 0 msb lsb 1 0 * * * * * * irrelevant 0 msb lsb 1 1 * * * * * * irrelevant 1 msb lsb 0 0 * d d d d * irrelevant 1 msb lsb 1 0 ***** * irrelevant
description of functions (1) register the BU9728AKV has a command / data register configured of eight bits. serial data is read in 8-pulse units of the sck clock. if the data read to the register is display data (c / d is low at the 8th clock pulse of sck), it is written to the ddram, and if the data is command data (c / d is high at the 8th clock pulse of sck), it is output to a command decoder and used to control the BU9728AKV. (2) address counter the address counter indicates the ddram address. when the set address is written to the command / data register, the address data is automatically sent to the address counter. after the data is written to the ddram, the address counter is automatically incremented by either + 1 or + 2. the amount by which the counter is incremented is determined automatically, based on the following statuses: 8 bits written to ddram (c / d low at 8th clock pulse of sck) ? + 2 4 bits written to ddram (c / d high at 8th clock pulse of sck) ? + 1 when the address counter reaches 1fh, it will be reset back to 00h the next time it is incremented. (3) display data ram (ddram) the display data ram (ddram) is where displays are stored. the capacity of the ddram is 32 addresses 4 bits. the illustration below shows the relationship between the ddram and the display positions. ddram addresses set in the address counter are in hexadecimal format and are indicated as follows. (example) for a ddram address of ?4?(display position: seg 20 ) 7 standard ics BU9728AKV 00 0 1 2 bit ddram address 3 com 0 com 1 com 2 com 3 seg 0 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 29 seg 30 seg 31 01 02 03 04 05 06 07 1d 1e 1f ac 4 msb lsb ac 3 ac 2 ac 1 ac 0 1 msb lsb 0 1 0 0 1 4
8 standard ics BU9728AKV the display data input to the command / data register (when c / d is low) is written to the ddram address and the address consisting of the specified address + 1, which are indicated by the upper four and lower four bits of the data, respectively. the four bits of the display data are written sequentially, starting from the msb, to the msb of the ddram bits. if the rewrite ddram command is input (c / d is high), the four bits of the display data in the rewrite ddram command are written to the specified ddram address. the four bits of the display data are written sequentially, starting from the msb, to the msb of the ddram bits. (4) timing generator connecting rf between osc 1 and osc 2 causes the internal oscillator circuit to start oscillating, and generates a dis- play timing signal. the oscillator can also be started by inputting an external clock. (5) lcd drive power supply the lcd drive power supply is generated by the BU9728AKV. the lcd drive voltage (v lcd ) is supplied by v dd - v 3 , and the power supply is generated by v 1 = 2 ?v lcd / 3, v 2 = v lcd / 3. if an external bleeder resistance is used to supply the lcd drive voltage externally, the following relationship must be observed: v dd = v 1 ^ v 2 ^ v 3 ^ v ss (6) lcd drive circuit the lcd drive circuit is configured of four common drivers and 32 segment drivers. when oscillation begins, select- ed waveforms are output automatically for valid common outputs by the common counter, and de-selected wave- forms are output for other outputs. for segment outputs, drive waveforms are output automatically by the display data and common counter. the following page shows examples of common / segment output waveforms. (bit3 bit0) (bit3 bit0) d7 msb lsb d6 d5 d4 d3 d2 d1 d0 specified address specified address + 1 (bit3 bit0) 1 msb lsb 0 0 * d3 d2 d1 d0 rewrite ddram command display data fig. 3 rf oscillator circuit osc 1 osc 2 rf fig. 5 example of connection when using internal power supply v dd v 1 v 2 v 3 v ss fig. 6 example of connection when using external power supply v dd v 1 v 2 v 3 v ss fig. 4 external clock input osc 1 osc 2 open exit clock input
9 standard ics BU9728AKV lcd drive waveforms frame cycle v dd com 0 com 1 com 2 com 3 v 1 v 2 v 3 v dd v 1 v 2 v 3 v dd v 1 v 2 v 3 v dd v 1 v 2 v 3 v dd v 1 v 2 v 3 v dd com 0 com 1 com 2 com 3 0 0 0 0 display none of the segments com 0 to 3 . 1 0 0 0 display segment which applies to com 0 . 0 1 0 0 display segment which applies to com 1 . 0 1 0 1 display segments which apply to com 1 and com 3 . 1 1 1 1 display segments which apply to com 0 to com 3 . v 1 v 2 v 3 v dd v 1 seg 0 seg 31 v 2 v 3 v dd v 1 v 2 v 3 v dd v 1 v 2 v 3 ~
10 standard ics BU9728AKV external dimensions (units: mm) vqfp48 0.5 0.125 0.1 0.10 0.2 0.1 9.0 0.3 7.0 0.2 9.0 0.3 7.0 0.2 48 37 1 12 13 24 25 36 0.5 1.425 0.1 0.10
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